Enhancing the security Random Logic Locking

• Henry Grant, Computer Science, University of Delaware

• Satwik Patnaik, Electrical and Computer engineering, University of Delaware

Logic locking is a hardware security technique used to protect integrated circuits (ICs) from various forms of attacks, such as intellectual property (IP) theft, reverse engineering, and hardware Trojan insertion. The primary goal of logic locking is to ensure that a circuit functions correctly only when the correct key is applied. This is achieved by inserting additional logic gates, such as XOR or XNOR gates, into the design in a way that the circuit’s proper operation depends on a secret key. One notable form of logic locking is RLL (random logic locking) which randomly inserts the aforementioned gates into the circuit. The main problem with this form of locking is that when designs are locked with large key sizes, a locked design starts having multiple correct keys, which makes it easier for an attacker to obtain the original design because they have more options regarding what the correct key could be. Here I report that adding a bit of selectiveness into the random approach of adding these gates mitigates the problem of a large number of correct keys produced when designs are locked with a key size that is particularly large. This is done by only selecting certain wires within the design to lock. Then I use the SAT attack to check how many correct keys will work for the newly locked design and compare that to the amount of locked keys produced when designs are locked with RLL. Providing a way of reducing the number of correct keys will make for more secure locked designs against the threat of IP theft